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AHB Multi-Channel DMA Controller

The Digital Blocks DB-DMAC-MC-AHB Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with a unified AHB5 Master Read/Write interconnects. The DB-DMAC-MC-AHB excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, and 16.

The DMA Controller IP Core can serve as a general-purpose Programmable DMA Controller supporting many system memories and peripherals, or be sized to the user required number of DMA Engines, AMBA interconnect interfaces, and user application interfaces.

特色

1 - 16 Multi-Channel High Performance DMA Controller Engines:
High-Speed Finite State Machine Control
High Throughput to/from Memory & Peripherals via AMBA AHB on both small and large data sets
Configurable with Dual-Port, Single- or Dual-Clock FIFO
FIFOs user parameterized in Depth x Width
User program Control, Status, Diagnostics via AMBA AHB/APB Slave Interface
Scatter / Gather – supports non-contiguous data block transfers to a contiguous segment of memory and vice versa
AHB5 Master Read/Write Interfaces
Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
Programmable Data Burst Capability: 1, 4, 8, 16 on AHB/User Interfaces.
Variety of User DMA Transfer Control:
Hardware or Software Initiated Transfers
Link-List Processor for Autonomous & Chained Block Transfers
Arbiter with variety of Arbitration Modes
Interrupt Controller – Signaling DMA Transfer Done & Diagnostics
Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.