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Simple Micro APB Bus Controller
CoreABC is a simple, low gate count controller for Advanced Microcontroller Bus Architecture (AMBA®) advanced peripheral bus (APB) based designs. In particular, it is targeted to control CoreAI and CorePWM in mixed-signal applications, but it can be used to control any APB or APB3 bus IP core. CoreABC supports a comprehensive assembler-based configurable instruction set architecture and extensive and flexible configuration of size and feature options allowing it to be tuned to meet the resource constraints and processing power requirements of a wide variety of applications. The instructions executed are either held in a small internal ROM constructed from logic tiles ("hard" configuration), stored in RAM blocks internal to CoreABC ("soft" configuration), or in Fusion or SmartFusion devices, in on-chip nonvolatile memory ("NVM" configuration). The core is easy to configure and program offering efficient local control for use in real-time applications in Microsemi FPGAs.
The core consists of six main blocks:
* Instruction block
* Sequencer
* ALU and flags
* Storage
* ACM
* APB controller
* AMBA3 APB master interface controller
The core consists of six main blocks:
* Instruction block
* Sequencer
* ALU and flags
* Storage
* ACM
* APB controller
* AMBA3 APB master interface controller
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Block Diagram of the Simple Micro APB Bus Controller
Simple Micro APB Bus Controller IP
- Configurable CAN Bus Controller IP with Flexible Data-Rate
- Direct Memory Access Controller IP Core
- I2C Host / Device Bus Controller
- CAN 2.0 & CAN FD Bus Controller IP
- SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
- I2C Controller (AMBA APB <-> I2C)