The SHA-512 Fast IP Core provides a hardware implementation of the Secure Hash Algorithm (SHA-512). The SHA-512 algorithm belongs to a group of five secure iterative hash algorithms recommended by NIST as part of their Secure Hash Standard (FIPS 180-3). The SHA-512 hash can accept messages up to 2^128-1 bits in length and returns a 512-bit message digest.
The SHA-512 Fast IP Core provides a balance between high throughput and size. The Fast IP core comes with a 64/512-bit IO interface and integrated padding logic. The core is designed for applications that need high throughput, low latency, and reduced power consumption.
- Implements SHA-512 secure hash algorithm specified by NIST FIPS 180-3
- Synchronous 64/512-bit IO interface (byte oriented)
- Integrated padding logic
- High throughput requires only 82 clock cycles per 1024-bit hash block
- Small hardware footprint for reduced power consumption
- IPSec, Data Integrity & Authenticity (TLS/SSL), Digital Signatures & Financial Transactions (DSS)
- Device specific netlist or RTL Verilog/VHDL source code
- Verilog/VHDL simulation model and testbench
- User documentation
Block Diagram of the SHA-512 Fast IP Core