This hardware IP core features a full Secure Hash Algorithm SHA1.
- SHA-1 Secure Hash as defined in latest FIPS PUB 180-3.
- Compatible HMAC for Hash Message Authentication as per FIPS PUB 198.
- Fully verified with NIST test vectors.
- Power aware design with power off function.
- Minimum latency: 84 cycles per block of 512 bits.
- Continuous operation, no wait cycles needed.
- Fastest thoughput: hash up to 2.5 Gbps in a Virtex-5 FPGA (414 MHz).
- Full technical support up to successful client integration
- Documentation and design examples
- Complete Testbench
- Instantation Template