The HIP 3300 Serial RapidIO IP solution is a complete high-performance core that incorporates a logical layer, a transport layer, and a physical layer according to the RapidIO specification ver 2.1. HIP3300 IP core also supports I/O and message-passing. The core provides a Serial RapidIO interface on one side and ARM's AMBA 3 AHB, high performance interface on the other side of the core, allowing felxible and high performance communication with host CPU. Modular design of the IP core
allows easy implementation of add-on third party bus interfaces and/or other standard bus interface. IP core also has internal multi-channel DMA desciprot based, controller that fully exploits AHB protocol features and thus supports highest available data throughput and back to back packet transmissions.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.