MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
SDRAM DDR3/2 & LPDDR3/2 Hardened PHY - TSMC 80nm 80GC,LP_EMF
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin s DDRx and LPDDRx SDRAM Memory Controller IP.
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