Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
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RTP / UDP / IP Hardware Stack
The RTP / UDP / IP Hardware Stack IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor targeting low latency, full off-load from a processor, of Audio/Video Packet Processing. The RTP / UDP / IP Hardware Stack is a Verilog SoC IP Core targeting Xilinx/Altera/Lattice FPGAs and ASIC/ASSP devices.
查看 RTP / UDP / IP Hardware Stack for Raw, Uncompressed RGB/YUV Video Streams 详细介绍：
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Block Diagram of the RTP / UDP / IP Hardware Stack for Raw, Uncompressed RGB/YUV Video Streams
