USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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ROM Compiler IP, UMC 0.18um LL process
UMC 0.18um low leakage(LL) Logic process synchronous Via1 ROM memory compiler.
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