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RISC-V-based SoC template
IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or ASIC. It supports stand-alone and booting modes, and can use internal RAM or an external DDR controller via L1/L2 cache systems.
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Block Diagram of the RISC-V-based SoC template
![RISC-V-based SoC template Block Diagam](http://www.design-reuse.com/sip/blockdiagram/48277/20201101010124-main-IoB-SoC_block_diagram.png)
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- 64-bit RISC-V Application Processor Core
- Dual-issue Linux-capable RISC-V core