Register Indirect RAM Access

The Veriest Register Indirect RAM Access Design IP provides a bridge between the embedded AMBA AHB bus and a configurable number of embedded SRAM devices for test, initialization and other low bandwidth purposes. The Veriest Register Indirect RAM Access is ideal for IP developers to provide access to shared RAMs in which the CPU needs to have limited access whereas another RAM client has priority access. After a simple register configuration setup by the CPU, the RAMs can be accessed for read and write through the AHB slave interface.

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