Reed Solomon Encoder / Decoder II
Throughput:
* Supports up to 10 Gbps with multiple core instantiation
* Provides 2.5-Gbps throughput for Stratix® series FPGAs
* Provides 1.28-Gbps throughput for Cyclone® series FPGAs
* Supports up to 16 interleaved channels
The RS Compiler II generates a fully parameterizable RS function, allowing you to set the following parameters:
* Number of bits per symbol (8)
* Number of symbols per code word (range: 204 to 255 )
* Number of check symbols per code word (range: 2 to 66)
* All valid field polynomials
The RS function offers the following other features:
* Intellectual property (IP) functional simulation models for use in Altera®-supported VHDL and Verilog HDL simulators
* Easy-to-use IP Toolbench interface: * Generates parameterized encoder or decoder
* Generates customized test bench and customized Tcl script
* Avalon®-ST interfaces
* DSP Builder ready
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