Rambus Crypto Accelerator AES-ECB–Medium Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumption compared to running the same algorithms in software.
The Crypto Accelerator Hardware Cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution, offering various levels of cryptographic acceleration performance.
They are easy to integrate into various SoC and FPGA architectures and development flows, and are all designed to maximize performance versus silicon area requirements. The Rambus IP core pass all NIST CAVP vectors. Several of the cores are also available in Differential Power Analysis (DPA) protected versions, extensively validated using the standardized Test Vector Leakage Assessment (TVLA) methodology. These Crypto accelerator cores are portable to any FPGA or ASIC technologies.
- Superior performance cryptographic cores optimized for performance, area, and security applications
- Technology and node independent RTL source code design
- Synchronous design and interface allows easy integration in various SoC architectures
- Superior Cryptopraphic protection
- Use with any ASIC or FPGA Technology and node independent
- Configurable Cryptographic Core: Verilog RTL reference design
- Synthesis Inputs: SDC constraint file suitable for FPGA or ASIC synthesis
- Full Documentation: Specification documents and Integration guides
- Functional Testbench: NIST-compliant test vectors
- Government, Automotive, Military, Edge, IoT, Machine Learning (ML), Artifical Intelligence (AI), Semiconductor, Processors, Cryptocurrency
Block Diagram of the Rambus Cryptographic Accelerator Core AES-FBC–Medium