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Programmable PLL in TSMC 40nm
Low Noise Programmable PLL Implemented in TSMC 40nm LP
特色
- 40nm TSMC Logic LP Process, 6 Metals Used
- Input Frequencies from 10MHz to 40MHz
- Output Clock Range: 5MHz up to 600MHz
- Power Down and Bypass Mode
- Long-Term Jitter Below 14psrms
- 11mW Power Dissipation
- No External Components Required
- Compact Die Area
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