The TRV301TSM40LP IP is a 1.1V low-power low-silicon-area 16MHz-to-2GHz Fractional-N Clock PLL implemented in TSMC Low-Power 40nm CMOS process technology. Its low loop filter bandwidth and low-frequency reference clock makes it especially suitable for use in clock synthesis for DAC, ADC and digital subsystems within wireless communication and broadcast integrated circuit chipsets (LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM, etc).
- 16MHz-to-2GHz PLL Output Coverage
- Scalable Power Consumption
- Three independent programmable PLL outputs
- Internal Calibration Engine and Convergence Algorithm
- Fully-integrated 165kHz loop filter
- 13MHz to 52MHz Crystal Oscillator Reference Support
- Low-power and low-area fully-featured 16MHz-to-2GHz Clock PLL with programmable outputs and integrated calibration engine and tuning voltage convergence logic.
- Behavioural Models
- Timing Models
- GDSII Layout Database
- Netlist for LVS verification
- Usage and Integration Guidelines
- PLL is suitable for embedding in ASIC and SoC subsystems for:
- LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM and many more
Block Diagram of the 40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL