Cap-less 106 dB dynamic range ADC with low power mode and ultra low latency capability
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40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
The TRV301TSM40LP IP is a 1.1V low-power low-silicon-area 16MHz-to-2GHz Fractional-N Clock PLL implemented in TSMC Low-Power 40nm CMOS process technology. Its low loop filter bandwidth and low-frequency reference clock makes it especially suitable for use in clock synthesis for DAC, ADC and digital subsystems within wireless communication and broadcast integrated circuit chipsets (LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM, etc).
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Block Diagram of the 40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
