You are here:
Power On Reset (POR)
特色
- The Power on Reset circuit, hcl_gf40_por_1p8_3p3 has three configuration and their specifications are listed as below:
- Mode0 1.8 and Mode1 3.3 V supply mode
- MODE 0 Rise and Fall Delay on a slope of 1V/1µs 2.184 and 3.194 µs respectively.
- MODE 0 Rise and Fall Delay on a slope of 1V/100ns 1.284 and 3.144 µs respectively.
- MODE 1 Rise and Fall Delay on a slope of 1V/1us 5.202 and 8.483 µs respectively.
- MODE 1 Rise and Fall Delay on a slope of 1V/100ns 5.068 and 8.279 µs respectively.
- Quiescent Current 5.176 µA
- Area 200 um X 200 um
- Technology Node: GF 40nm 1P7M
- Note: The POR hcl_gf40_por_1p8_3p3 can be configured for both the modes and just for one of the modes Mode 0 and Mode 1 which can work on different supply voltages VDDA and VBAT as shown in Figure 1
查看 Power On Reset (POR) 详细介绍：
- 查看 Power On Reset (POR) 完整数据手册
- 联系 Power On Reset (POR) 供应商
Block Diagram of the Power On Reset (POR)
Power IP
- Multi-Protocol Crypto Packet Engine, Low Power, Bus Attached
- Low-Latency SerDes PMA
- Power Deliver Network Monitoring and Droop Detection
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP
- Complete USB Type-C Power Delivery PHY, RTL, and Software