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PLBv46 to PCI Full Bridge
The PLBv46 to PCI Full Bridge design provides full bridge functionality between the Xilinx PLB and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI) bus.
The PCI32 core provides an interface with the PCI bus. Details of the LogiCORE™ IP PCI32 core operation is found in the Xilinx LogiCORE IP PCI32 Interface v3, in the Xilinx LogiCORE PCI32 Interface v4 Product Specification, and in the Xilinx LogiCORE IP PCI v3.0 and v4.1 User Guides.
Host bridge functionality (often called North bridge functionality) is an optional functionality. Configuration Read and Write PCI commands can be performed from the PLB-side of the bridge. The PLBV46 PCI Bridge supports a 32-bit/33 MHz PCI bus only.
The PLBV46 PCI Bridge design has parameters that allow customers to configure the bridge to suit their application. The parameterizable features and exceptions to the support of PCI commands are discussed in the data sheet.
Available to all licensees of the PCI32 LogiCORE IP cores.
The PCI32 core provides an interface with the PCI bus. Details of the LogiCORE™ IP PCI32 core operation is found in the Xilinx LogiCORE IP PCI32 Interface v3, in the Xilinx LogiCORE PCI32 Interface v4 Product Specification, and in the Xilinx LogiCORE IP PCI v3.0 and v4.1 User Guides.
Host bridge functionality (often called North bridge functionality) is an optional functionality. Configuration Read and Write PCI commands can be performed from the PLB-side of the bridge. The PLBV46 PCI Bridge supports a 32-bit/33 MHz PCI bus only.
The PLBV46 PCI Bridge design has parameters that allow customers to configure the bridge to suit their application. The parameterizable features and exceptions to the support of PCI commands are discussed in the data sheet.
Available to all licensees of the PCI32 LogiCORE IP cores.
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