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Phase Locked Loop (PLL) Frequency Synthesizer Core
For general purpose Phase Locked Loops (PLL), ASIC designers have to rely on analog VCOs until today. Now Cologne Chip has come up with a fully digital approach: C3-PLL-2, an IP core for frequency synthesizer applications.
C3-PLL-2 relies on the DIGICC design concept of Cologne Chip, which makes it possible to be easily implemented in all process technologies as a fully digital circuitry. The lock time of the PLL is very low while the used circuit area is smaller than that of competing technologies. Because of its pure digital nature the C3-PLL-2 does neither require any additional pad or pin nor external or internal loop capacitors. External filters for the supply voltage are normally not needed. A patent is pending for this innovation of Cologne Chip.
C3-PLL-2 is based on C3-PLL-1 and contains additional read/write registers with address decoder, a predivider and a post-scaler.
C3-PLL-2 relies on the DIGICC design concept of Cologne Chip, which makes it possible to be easily implemented in all process technologies as a fully digital circuitry. The lock time of the PLL is very low while the used circuit area is smaller than that of competing technologies. Because of its pure digital nature the C3-PLL-2 does neither require any additional pad or pin nor external or internal loop capacitors. External filters for the supply voltage are normally not needed. A patent is pending for this innovation of Cologne Chip.
C3-PLL-2 is based on C3-PLL-1 and contains additional read/write registers with address decoder, a predivider and a post-scaler.
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