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PCMCIA IP Host Controller
The Mentor Graphics PCMCIA core provides an efficient and easy-to-use interface to devices that are PCMCIA card 2.1 compliant. The core generates read/write cycles for attribute memory,common memory,and I/O modes. The core is designed to interface to the processor through aCoreFrameîbusinterface. The CoreFrame bus interface is anon-pipelined interface incorporating address, data, read strobe, write strobe, and a wait signal. Interrupt status and
maskingregisters are provided to enable polled or interrupt driven firmware to service the interrupts. Particular events on the PCMCIA card interface can be programmed to generate an interrupt to the processor. The core includes programmable timing control registers to support a wide range of operating frequencies. PC cards can be memory mapped to simplify firmware.
maskingregisters are provided to enable polled or interrupt driven firmware to service the interrupts. Particular events on the PCMCIA card interface can be programmed to generate an interrupt to the processor. The core includes programmable timing control registers to support a wide range of operating frequencies. PC cards can be memory mapped to simplify firmware.
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