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PCIe 2.0 PHY TSMC 40LP
The Innosilicon PCIE2.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for PCIE2.0 Super-Speed standard from Intel. The PHY supports PCIE2.0(5Gb/s/2.5Gb/s) physical layer specifications.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
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PCIE 2.0 PHY IP
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 5.0 SerDes PHY
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- USB 3.0 SATA 3.0 PCIe 2.0 XAUI MultiPHY
- 1G-16G SerDes IP, Supports (PCIe Gen4/3/2/1, JESD204B) (Silicon Proven in TSMC 28HPC+/HPC/HPM)
- PCIe Gen2 PHY