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NVMe Target IP Core
The IntelliProp IPC-NV163A-DT NVMe Target IP core allows companies to build high speed NVMe based storage products. The IPC-NV163A-DT provides a hardware accelerated queue management interface for NVMe commands and completions as well as provides the NVMe controller register interface for host communication and controller management.
The IPC-NV163A-DT is designed to be integrated into an NVMe-compliant device application. The NVMe Target IP core manages multi-queue command fetching and completion posting via an internal controller register interface. Multi-queue command fetching is automated by state-machines internal to the IP core. As commands are fetched from host memory, the commands are filtered by type and provided to the controller application software via a simple context FIFO interface. As the controller application software completes command processing, the controller application software can complete the command via a simple completion context interface in the IP core. Once a completion context push is made to the IP core completion FIFO, the IP core internal state-machines automate the NVMe completion queue context transfer and update all pointer and phase information without software intervention. This automated command fetching and completion posting interface provides very low latency interface to the controller application software which is required for maximum IOPs and data bandwidth.
The IPC-NV163A-DT is designed to be integrated into an NVMe-compliant device application. The NVMe Target IP core manages multi-queue command fetching and completion posting via an internal controller register interface. Multi-queue command fetching is automated by state-machines internal to the IP core. As commands are fetched from host memory, the commands are filtered by type and provided to the controller application software via a simple context FIFO interface. As the controller application software completes command processing, the controller application software can complete the command via a simple completion context interface in the IP core. Once a completion context push is made to the IP core completion FIFO, the IP core internal state-machines automate the NVMe completion queue context transfer and update all pointer and phase information without software intervention. This automated command fetching and completion posting interface provides very low latency interface to the controller application software which is required for maximum IOPs and data bandwidth.
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