55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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NVM Express IP Core
Typical storage controllers are composed of a communication interface and a Nandflash controller. In this case, all the data flow is managed by the external host processor. This architecture is not able to sustain high performance applications. The NVMe IP core is a powerful data transfer manager to be integrated in the PCIe SSD Controller between the communication interface and the Nandflash controller, therefore off-loading the host CPU. It is fully NVM Express 1.0d compliant.
SSD and server manufacturers benefit from this new technology thanks to the driver standardization. All PCIe SSDs which are NVM Express compliant will be supported by a unique driver, whic leads in a ease of use and a software development cost reduction.
Using pre-validated NVMe IP core, allows to greatly reduce Time-To-Market for storage OEM who wants to benefit from a powerful data transfer manager. The NVMe IP core is full featured, easy to use into FPGA and SoC designs.
SSD and server manufacturers benefit from this new technology thanks to the driver standardization. All PCIe SSDs which are NVM Express compliant will be supported by a unique driver, whic leads in a ease of use and a software development cost reduction.
Using pre-validated NVMe IP core, allows to greatly reduce Time-To-Market for storage OEM who wants to benefit from a powerful data transfer manager. The NVMe IP core is full featured, easy to use into FPGA and SoC designs.
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Block Diagram of the NVM Express Host IP Core
Video Demo of the NVM Express Host IP Core
This is the NVM Express demo from IP-Maker demonstrated at Flash Memory Summit 2022, Santa Clara, CA. The NVMe IP is integrated in a FPGA-based board including all the mandatory features of the NVM Express specification 2.0. NVMe protocol is observed with a protocol analyzer from Teledyne Lecroy.