Multi-Link Multi-Protocol SerDes - PHY IP for PCIe 3.0 TSMC 16FF+GL

Cadence 16Gbps Multi-Link and Multi-Protocol PHY - silicon proven, high-speed SerDes PHY IP, designed to simultaneously run different protocols at different clock signal rate on a per lane basis.
The 16Gbps Multi-Link and Multi-Protocol PHY is the latest member of Cadence family of multi-protocol SerDes (Serializer/Deserializer) IPs. It is architected as a hard PHY macro consisting of a Physical Media Attachment (PMA) layer and a soft Physical Coding Sublayer (PCS).
The PHY macro operates with frequency range support from 1.25Gbps to 16Gbps, and is compliant with PCIe 4.0, USB 3.1 (Gen1 and Gen2), 10G-KR, SFP+, RXAUI, XAUI, QSGMII/SGMII, SATA 3 specifications. The 16Gbps Multi-Link and Multi-Protocol PHY can be configured by Cadence to be a full Multi-Protocol PHY or a PHY that supports a subset of standards, where the different protocols can be ordered as options.
This PHY IP can quickly and easily integrate into any SoC, and connect seamlessly to Cadence, or third party, PIPE 4.2-compliant controllers. Multiple test features, such as an EyeSurf (non-destructive on-chip oscilloscope) are embedded to this macro and easily accessible by the end-user.
Cadence 16Gbps Multi-Link and Multi-Protocol PHY provides a cost-effective, protocol-versatile, and low-power solution for today enterprise-level data communications, networking and storage applications.

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