You are here:

Multi-Gigabit Fibre Channel Controller

The Gigabit / 2-Gigabit FC-2 Core provides a generic solution for 1Gbps and 2Gbps Fibre Channel applications. The core is designed to support standard Fibre Channel applications such as point-to-point and fabric interconnect. On the Client side, the Core implements a 16-Bit FIFO interface running asynchronously from the Fibre Channel line clock. The FC-2 Layer provides services such as CRC generation / check, Fibre Compliant frames generation, buffer-to-buffer credit with necessary Fibre Channel timers and link set-up FC_PORT state machine.
The FC-1 function implements the line coding (8B/10B), maintains DC balancing on the line, performs frame encapsulation, Fibre Channel Primitive Sequences generation / decoding, receive data alignment and link synchronization. On the line interface, the Core implements a standard 10-Bit or 20-Bit interface that can be connected to any commercial or embedded SERDES (SERializer / DESerializer). The Core can be targeted to programmable devices, for system prototyping and validation and ASIC technologies.

特色

Dynamically configurable to support Gigabit (1.06Gbps Baud rate) or 2 Gigabit (2.12Gbps Baud rate) Fibre Channel applications
Fibre Channel logic operates at rates up 106.25MHz
Seamless interface to commercial SERDES device or Fibre Channel control via a standard 10-Bit (Gigabit Operation) or 20-Bit (One and Two Gigabit Operation) interface
Built-In client interface FIFO providing rate and clock decoupling
Simple 16-Bit FIFO interface to user client application compatible with Altera Atlantic specification
CRC-32 checking at 106.25MHz wire speed using a multi-stage CRC calculation architecture
Optional CRC check and correction on the Core transmit path controllable on a frame by frame basis
Frame minimum and maximum length verification with long frame truncation and error indication
Link coding implemented with 8B/10B providing DC balanced bitstream for efficient SERDES operation
Maintain 8B/10B current disparity rules with automatic correction using positive or negative encoded EOF primitives
Negative encoded K28.5 Comma detection with automatic optical stream alignment
Implements FC-1 link synchronization with Loss of Synchronization indication
Implements Fibre Channel FC_PORT Port control state machine with programmable timers
Core configurable as N or F Fibre Channel port with automatic Fabric frames discard (N Port configuration)
Provide FC Transport support for point-to-point Fibre Channel applications
Support any Fibre Channel Traffic Class and Frame termination condition
Implement Buffer-to-Buffer Credit management with credit recovery, credit reset and automatic R_RDY, BB_SCr and BB_SCs primitives generation
Programmable 16-Bit credit recovery timer
Programmable Transmit and Receive FIFO depth
Implements processor control interface with 32-Bit statistic counters and configuration registers
Simple handshake user application FIFO interface with fully programmable depth and threshold levels ensuring data rates of 2Gbps with full back-to-back frame transfer support
Available on Altera StratixGX devices with integrated SERDES providing a single chip Fibre Channel port controller implementation

可交付内容

The core is optionally delivered in generic synthesizable VHDL or Verilog source code (For use in FPGA / CPLD or ASIC technologies) or as a FPGA / CPLD netlist.