MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3A, N3E)
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MIPI M-PHY v3.1 IP,在 TSMC 28HPC+ 中经过硅验证
MIPI M-PHY Gear 3 IP符合由SerDes PHY产品简介联盟定义的最新的MIPI储存IP规范解决方案规范,M-PHY v3.0规范和UniPro v1.8规范和通用闪存(UFS)v3.0规范。这个IP具有高带宽能力的串行接口技术,专为移动设备设计,支持高达5.8Gear3的数据传输速率,具有低引脚数和高效的功率效率。MIPI M-PHY Gear 3 IP兼容RMMI接口,能够适配UniPro控制器和UFS控制器。MIPI M-PHY通过低成本的内置自测试(BIST)提供了强大的可测试性,以及提供针对嵌入式系统的接收机眼数据监控和调试功能。
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Block Diagram of the MIPI M-PHY v3.1 IP,在 TSMC 28HPC+ 中经过硅验证

MPHY IP IP
- MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3A, N3E)
- MIPI M-PHY - TSMC 40nm
- UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0
- MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)