LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
MIPI HSI Controller IP Core
Three flavors of the IP are currently available, namely, with support for AHB, AXI or OCP system buses. The IP’s internal registers are accessible through programmed IO transactions, in which case the IP functions as a bus slave. All data transfers between the SoC’s system memory and HSI interface happen either in PIO mode or in DMA mode as programmed by the driver/firmware.
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Block Diagram of the MIPI HSI Controller - (High-Speed Synchronous Serial Interface)
silicon IP IP
- Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks
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- 32kHz Ultra-Fast-Lock IoT PLL
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