The HIP 3510 is a highly configurable, synthesizable digital IP core, used to exchange pixels and command data between a video source (host processor) and a display
peripheral. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, HIP3510 is fully compliant to MIPI
Alliance's DSI, DPI-2, and DCS standards, as well as to AMBA's AHB specification. The video data is provided from an external D-PHY using either the HS (High Speed) or LP (Low Power) reception modes via a PPI interface, then processed by the HIP 3510 logic according to the DSI and DCS specifications., The output video data stream is sent to the DPI-2 or DBI interface.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.