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MIPI D-PHY Transmitter IP Core
The MIPI D-PHY Transmitter IP Core is compliant with the MIPI Alliance Standard for D-PHY. The MIPI D-PHY Transmitter is configured as a MIPI master and consists of 4 lanes: 1 Clock lane and 3 data lanes, which makes it suitable for display interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
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Block Diagram of the MIPI D-PHY DSI TX (Transmitter) IP
MIPI D-PHY Transmitter IP
- MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
- MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL
- MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)