180nm FTP Non Volatile Memory for Standard CMOS Logic Process
MACsec 10G/25G
The core is configurable to have multiple Security Entities, SecYs, in a single IP to support multiple Connectivity Associations per port for traffic differentiation, and is prepared for easy interfacing with Comcores or third-party MAC, PCS and TSN Switch IPs.
The MACsec Engine implements 64-bit AXI-S input and output data interfaces. It offers flexibility on integration with IEEE 1588 PTP Timestamping Unit (TSU). It additionally includes a software tool for MACsec Key Agreement Protocol IEEE 802.1X integration.
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Block Diagram of the MACsec 10G/25G
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