LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL

The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be easily fabricated and implemented in a GVI, LVDS or MIPI DSI system. For GVI/LVDS system, Macro consists of multi-transmitter channels and one SU unit. The speed of transmitter macro is up to 4.0Gbps and can be configured to GVI (CML) or LVDS mode. For MIPI DSI system, a DSI configuration includes a Clock Lane Module and four Data Lane Modules.

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