LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / throughput combinations, allowing the designer to choose the smallest core that satisfies the desired clock/throughput requirements. Each core contains the base AES core AES1 and is available for immediate licensing.
The design is fully synchronous and available in both source and netlist form.
- Small size: LRW3-18.2 starts at less than 50,000 ASIC gates at throughput of 18.2 bits per clock
- Completely self-contained: does not require external memory
- Supports both encryption and decryption
- Includes key expansion
- Support for Liskov-Rivest-Wagner encryption and decryption (LRW)
- 128+128 and 256+128 bit LRW keys supported.
- Easily parallelizable for even higher data rates
- Flow-through design
- Test bench provided