You are here:
LPDDR3 PHY
The DDR4 multi-modal PHY is a DFI 3.1 compliant memory interface that supports both UDIMM and RDIMM modules as well as DRAM–on-motherboard topologies, making it suitable for a broad range of enterprise and consumer applications. Our PHY consists of a Command/Address (C/A) block, Clock and Power Management block and Data (DQ) macro cells to create a 72 bits wide channel. It is fully characterized and contains all of the necessary components for robust operation and is available in GF 28SLP and SS 28 LPP processes.
查看 LPDDR3 PHY 详细介绍:
- 查看 LPDDR3 PHY 完整数据手册
- 联系 LPDDR3 PHY 供应商