Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
Low power 9 bit cyclic ADC
特色
- The ADC conversion is divided into three phases. In each of the phases three bits are obtained; in Phase I the three most significant bits are obtained (MSBs), in Phase II the three middle bits and in Phase III the three least significant bits (LSBs). The voltage swing at the output of the operational amplifier is adaptive and it depends on the conversion phase, accounting for the drop of supply voltage during the conversion cycle. Operational amplifier has a built-in slew rate (SR) detection circuit which dynamically controls the amplifier current and optimizes power consumption and speed.
优势
- Low power consumption, insensitivity to power supply variations
可交付内容
- Schematic and layout design(GDS) for chosen 180 nm technology
应用
- Low power applications, low sampling rate, ADC, energy harvesting systems
Block Diagram of the Low power 9 bit cyclic ADC

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