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Low Noise Programmable PLL
This customisable PLL has been designed for use with high performance A/D converters where low jitter clock generation is critical to the success of applications such as DVB, Cable Modem and Wireless LAN.
特色
- 40nm TSMC Logic LP Process, 6 Metals Used
- 1.1V and 2.5V Power Supply
- Input Frequency range: 9.6MHz - 150MHz
- Comparison Frequency range (Fcmp): 9.6MHz –
- 40MHz
- VCO frequency Range: 600MHz – 1300MHz
- 3 independent Programmable Output Clocks
- Output Clock Range at clkout[1:0] 9.53MHz –
- 600MHz
- Output clock range at clkout[2] 4.72MHz – 600MHz
- Power Down and Bypass Mode
- Low Long Term Jitter < 8ps rms (FVCO=1300MHz,
- Fcmp>19.2MHz)
- Low Long Term Jitter < 11.5ps rms (FVCO=1300MHz, 9.6MHz<Fcmp<19.2MHz)
- Power Dissipation 4 - 9mW
- No External Components Required
- Compact Die Area
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