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Low Noise Fractional PLL - GlobalFoundries 65nm
This customisable PLL has been designed for use with high performance A/D converters where low jitter clock generation is critical to the success of applications such as DVB, Cable Modem and Wireless LAN.
A fractional PLL is used yielding excellent phase noise performance. The PLL is designed to provide excellent jitter performance while also maintaining low current consumption in a very small area.
The PLL includes built in self calibration which is run when the desired VCO frequency is changed.
To save area an external bandgap is used to supply a low noise reference current to this block.
The PLL is implemented in a standard 6 metal 65nm basic logic process with no analog options. It is readily portable to any similar manufacturing process or can be customized upon request.
A fractional PLL is used yielding excellent phase noise performance. The PLL is designed to provide excellent jitter performance while also maintaining low current consumption in a very small area.
The PLL includes built in self calibration which is run when the desired VCO frequency is changed.
To save area an external bandgap is used to supply a low noise reference current to this block.
The PLL is implemented in a standard 6 metal 65nm basic logic process with no analog options. It is readily portable to any similar manufacturing process or can be customized upon request.
特色
- 65nm Global Foundries Logic LP Process
- No Analog Options
- 1.2V Power supply
- Input Frequency: 10MHz – 40MHz
- Comparison Frequency: 1MHz – 40MHz
- VCO Frequency: 240MHz – 320MHz
- 21-Bit Output Frequency Resolution (0.1ppm)
- Four Independent Output Dividers
- Output Clock Range 1 – 80MHz and 120-160MHz
- Power Down and Bypass Mode
- Programmable Loop Filter
- Long Term Jitter < 14psrms
- Period Jitter < 5psrms
- Power Dissipation < 2mW
- No External Components Required
- Very Small Die Area: 0.05mm2
应用
- Clock Generation for Digital IC and Serial Communications
- Clocking of A/D and D/A Converters
- Low Power and Low Noise Clock Generation
Block Diagram of the Low Noise Fractional PLL
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