180nm FTP Non Volatile Memory for Standard CMOS Logic Process
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Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks
High bandwidth PLL with accurately spaced 16-phase output clocks. Low Power/ Low Area hard macro with industry leading jitter performance for its power/area class.
Product is currently available in the following processes:
- TSMC - 28nm (HP, HPM, HPL, LP), 40nm (G, LP), 65nm (GP, LP), 90nm (G, LP), 130nm (G), 180nm
- Global Foundries - 40nm (G, LP), 65nm (GP, LP)
- IBM - 65nm (G, LP), 130nm, 180nm
- SMIC - 65LL, 90G, 110G, 130G
- ST - 90G
Product is currently available in the following processes:
- TSMC - 28nm (HP, HPM, HPL, LP), 40nm (G, LP), 65nm (GP, LP), 90nm (G, LP), 130nm (G), 180nm
- Global Foundries - 40nm (G, LP), 65nm (GP, LP)
- IBM - 65nm (G, LP), 130nm, 180nm
- SMIC - 65LL, 90G, 110G, 130G
- ST - 90G
特色
- 100MHz up to 1.1GHz input/output frequency range
- Static phase-phase variation better than +-1.8% of output period
- Optional 8-phase output mode for power savings
- Small footprint (0.03mm^2)
- Low power (<5mW @ 800MHz)
- Low jitter: Long Term Jitter < 3% of output period (p-p, 6-sigma)
- Low jitter: Period Jitter < 1.5% of output period (p-p, 6-sigma)
- Built-in supply decoupling
- Simple digital control interface
优势
- Accurate generation of accurate 16-phase clocks can replace a DLL in many calibration systems
- High bandwidth PLL quickly adjusts to track input phase variations while filtering high frequency input noise to minimize phase-phase disturbances
- No external components required
- No additional supply decoupling required
- Loop automatically adjusts for any input frequency, so no complicated programming is required
可交付内容
- GDSII
- CDL Netlist (MG Calibre Compatible)
- Functional Verilog Model
- Liberty timing models (.lib)
- LEF
- Application Note
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