The IEEE 802.11n/ac/ax LDPC Decoder Core performs iterative decoding of channel data that has been encoded as described in the IEEE Std 802.11n/ac/ax standard.
- Code length: 648, 1296, 1944.
- Code rates: 1/2, 2/3, 3/4, 5/6 (for each code length).
- Programmable number of iterations.
- Internal convergence test stops the decoder when data is fully recovered (0 errors), to save power and increase throughput.
- High throughput support - up to 3 Gbps.
- Based on proprietary architecture, to reach high throughput with low area.
- Built in power saving features for low power design.
- Code synthesizable to ASIC and FPGA.
- * high throughput
- * low area
- * low power features
- * scalable clock frequency
- * slicon proven
- Verilog/VHDL source code.
- Extensive testing environment (test bench + stimuli generator).
- Matlab model.
- Synthesis script for Synopsys Design Compiler
- Detailed documentation.