Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
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LDO Regulator in TSMC 65nm
The Regulator has been designed to provide stable output in both low-drop and high-drop operation while maintaining minimum ripple on supply lines in the presence of large load current spikes inherent to high speed mixed signal circuits.
特色
- 65nm 6 Metal CMOS (No Analog Options)
- 2.5V through 1.45V Input Voltage
- 1.3V Output Voltage
- 150mA Load Current
- Wide Range Power Supply from 1.6V to 3.3V
可交付内容
- Detailed datasheet
- Integration guidelines
- Flatten netlist in standard format
- Physical layout in GDSII format
- Verilog/VHDL behavioral models
- Footprint in standard format
- Integration support services
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regulator power management
- Linear Voltage Regulator - High Input Voltage (30V), Output Load up to 5mA XFAB 0.35 μm
- Capless LDO voltage regulator (130 nm, 20 mA, excellent load transient)
- LDO Differential Feedback Capless Linear Regulator Series( Vin = 1.8-5.5V; Vo = 0.6-3.6V; Io = 20mA ) - TSMC 55nm
- LDO Differential Feedback Capless Linear Regulator Series( Vin = 1.8-5.5V; Vo = 0.6-3.6V; Io = 50mA ) - TSMC 40nm
- LDO Differential Feedback Capless Linear Regulator Series( Vin = 1.8-5.5V; Vo = 0.6-3.6V; Io = 50mA ) - TSMC 55nm
- 10mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm