DXTP GPU, and advanced graphics and compute acceleration for power constrained devices
You are here:
JESD207 RFIC IP
JESD207 RFIC is full-featured, easy-to-use, synthesizable design, compatible with JESD207 Compliant. Through its JESD207 RFIC compatibility,it provides a simple interface to a wide range of low-cost devices. JESD204 RFIC IIP is proven in FPGA environment. The host interface of the JESD207 RFIC can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
查看 JESD207 RFIC IP 详细介绍：
- 查看 JESD207 RFIC IP 完整数据手册
- 联系 JESD207 RFIC IP 供应商
JESD IP
- 1.8V/3.3V Switchable GPIO With 3.3V I2C Open Drain & Analog in TSMC 22nm
- A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
- Three-Speed Inline I/O Library with ODIO in TSMC 22nm
- IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
- A TSMC 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell