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JESD204B PHY
特色
- 1.25Gbps to 11.2Gbps continues per-lane data rate range
- 2 lanes, 4 lanes, 8 lanes to support
- Tolerate max +/-6000ppm input frequency offset
- Support 204B deterministic latency
- Support internal/external SYNC_N and SYSREF input
- 32bit/40bit selectable parallel data bus
- Independent and global channel power down control
- Programmable transmit amplitude
- 3 taps/2 taps selectable feed forward equalizer
- Adaptive CTLE + embedded DFE
- Build in self-test with PRBS pattern generation and checker
- Integrated on-die termination resistors:
- Flexible reference clock frequency
- Do not need any external component
- Avaliable for both flip chip and wire-bonding
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JESD204B PHY IP
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