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Internal LDO Regulator
U40LPLDO3P3V1 is a low DropOut(LDO) linear and high accuracy output regulator. By using CMOS technology, the quiescent current is less than 100uA over entire operation input voltage range. When shut down, the current is minimized to less than 1uA typically.
Power Good output is optionally provided to know when the LDO output voltage becomes more stable. Thermal Shut down Protection is also optionally provided to turn off LDO when junction temperature is over around 150℃.
Power Good output is optionally provided to know when the LDO output voltage becomes more stable. Thermal Shut down Protection is also optionally provided to turn off LDO when junction temperature is over around 150℃.
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Block Diagram of the Internal LDO Regulator
LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL