DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
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Interlaken Communication Controller
The Interlaken IP core is an efficient implementation of Interlaken Protocol version 1.1. Interlaken IP core is designed for flexibility, robustness, scalability and is available in 64(10-25 Gb/s), 128(20-25Gb/s), 256(40+ Gb/s) bit datapath variants.
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Block Diagram of the Interlaken Communication Controller
Interlaken IP
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Interlaken Controller
- Interlaken Controller
- Interlaken, 100G, 12 Lanes