MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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I3C Controller
Controller IP for the MIPI I3C interface
The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high performance required for today's leading-edge devices. One member of this family is the Cadence Initiator Controller IP for MIPI I3CSM. Compliant with the latest MIPI I3C specification and legacy compatible with I2CSM, the Controller IP is engineered to quickly and easily integrate into any mobile embedded system-on-chip (SoC) device and expand sensor communication capabilities with better power efficiency. Developed by experienced teams with industry-leading domain expertise, verified by silicon-proven and mature I2C IP and validated on a FPGA platform to reduce risk for designers, the IP will connect seamlessly to the Controller IP. The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, system, and peripheral IP.
The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high performance required for today's leading-edge devices. One member of this family is the Cadence Initiator Controller IP for MIPI I3CSM. Compliant with the latest MIPI I3C specification and legacy compatible with I2CSM, the Controller IP is engineered to quickly and easily integrate into any mobile embedded system-on-chip (SoC) device and expand sensor communication capabilities with better power efficiency. Developed by experienced teams with industry-leading domain expertise, verified by silicon-proven and mature I2C IP and validated on a FPGA platform to reduce risk for designers, the IP will connect seamlessly to the Controller IP. The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, system, and peripheral IP.
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