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I2C V2 Bus Interface
The MI2Cv2 provides an interface between a microprocessor and an I2C bus that conforms to V2.1 of the I2C bus specification.
It can be programmed to operate as either a master or a slave device and performs arbitration in master mode to allow it to operate in multi-master systems.
In slave mode, it can interrupt the processor when it recognizes its own 7-bit or 10-bit address or the general call address.
The design supports both High speed (Hs) and Fast / Standard speed (F/S) transfer rates. The user may define the transfer rate using either two clock enable signals or a pair of clock control registers similar to that offered in the Inventra™ MI2C and MI2CV designs.
It can be programmed to operate as either a master or a slave device and performs arbitration in master mode to allow it to operate in multi-master systems.
In slave mode, it can interrupt the processor when it recognizes its own 7-bit or 10-bit address or the general call address.
The design supports both High speed (Hs) and Fast / Standard speed (F/S) transfer rates. The user may define the transfer rate using either two clock enable signals or a pair of clock control registers similar to that offered in the Inventra™ MI2C and MI2CV designs.
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