The I2C slave to AXI4-LITE bridge IP core is a synthesizable Verilog HDL implementation of an I2C slave that provides a link between the I2C bus and AMBA AXI4-LITE. The core works as a Slave controller on the I2C bus, and a master controller on the ARM® AMBA® AXI4-LITE bus. On the I2C bus the slave acts as an I2C memory device where accesses to the slave are translated to AMBA accesses.
The I2C Slave to AXI4-LITE bridge IP core contains the optional APB slave interface for software configuration. I2C IP core client interface is standard I2C_SDA and I2C_SCL interface.