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Hyperbus Flash Memory Controller
Emerging high-performance applications demand increasingly fast read throughputs from NOR-flash memory devices. At the same time, the pin-count required to implement the memory subsystem should be restricted. The HyperBus flash controller was developed to satisfy the need for higher read/write performance while remaining sensitive to the pin-count constraints of modern microcontrollers. The HyperBus flash controller has the ability to satisfy the memory requirements for both volatile and nonvolatile memories in a large swath of high-performance applications.
The HyperBus flash Interface is a low pin count interface that achieves significantly higher perfor mance than legacy parallel and SPI interfaces for SPI based NOR flashes. This controller Interface involves a simple read/write protocol that is suitable for both memories and peripheral interfaces. Interestingly, this interface only requires an additional six pins more than the QSPI. The HyperFlash memories coupled with our Hyperbus flash controller provide a new standard for performance by delivering upto 333 MB/s using this 12-pin interface.
The HyperBus flash Interface is a low pin count interface that achieves significantly higher perfor mance than legacy parallel and SPI interfaces for SPI based NOR flashes. This controller Interface involves a simple read/write protocol that is suitable for both memories and peripheral interfaces. Interestingly, this interface only requires an additional six pins more than the QSPI. The HyperFlash memories coupled with our Hyperbus flash controller provide a new standard for performance by delivering upto 333 MB/s using this 12-pin interface.
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Block Diagram of the Hyperbus Flash Memory Controller
