MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
You are here:
High-speed ultra-low noise LVDS Driver
Seamless Microsystems’ (SMI) SMLVDS55 is an LVDS I/O driver operating at 2.4 GHz in TSMC 55nm ULP process. Using a core supply voltage of 1.2V and an IO supply of 2.5V, the LVDS driver achieves ultra-low substrate and supply noise operation and satisfies TIA/EIA-644 specifications. The drivers find suitable applications for low noise environments.
查看 High-speed ultra-low noise LVDS Driver 详细介绍：
- 查看 High-speed ultra-low noise LVDS Driver 完整数据手册
- 联系 High-speed ultra-low noise LVDS Driver 供应商
Block Diagram of the High-speed ultra-low noise LVDS Driver
LVDS IP
- Bi-Directional LVDS with LVCMOS
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane