DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
HDMI2.0 TX IP_UMC
Innosilicon HDMI TX IP consists of a digital controller and a physical layer.
The digital controller receives video, audio, synchronous signals, and control signals from the SoC logic and outputs encoded data to the physical layer.
The physical layer contains 1 clock channel and 3 data channels, PLL, and bias circuit. The clock channel transmits clock signals up to 340MHz to a receiver. Each data channel consists of a serializer and a driver. The serializer converts the parallel input data to 1-bit high speed serial stream and the driver converts the digital serial data to low swing differential signals with typical DC-coupled connection. The data rate is up to 6Gbps per channel. PLL generates the clocks required by data channels and the digital logic. The bias circuit generates voltage and current reference.
Innosilicon HDMI TX IP offers reliable implementation for HDMI interface, which can be integrated in the SoC used in multimedia devices.
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