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HDMI2.0 Receiver PHY & Controller
Innosilicon HDMI RX IP is composed of the digital controller, the PHY logic and physical layer. The digital controller receives video, audio, synchronous signals and the physical layer contains 3 data channels, a clock channel and bias circuit. The data channel consists of termination, level-shifter and equalizer circuit.
In each data channel, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The level-shifter changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. The input signals are reshaped by equalizer for frequency compensation. Then the serial stream is recovered and converted to 10-bit parallel output.
The PHY logic receives the recovered parallel data and clock signals of 3 data channels. These data are firstly synchronized to the same clock, then aligned to eliminate the channel skew and finally output to the controller for further process.
The HDMI receiver controller separates the incoming data stream into audio data, video data, and packet data information. The video interface can generate a variety of video formats including RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2, YCbCr 4:2:0. The receive audio interface includes up to four I2S output, for SPDIF outputs and a parallel audio output, providing support for HDMI 2.0 audio formats.
Innosilicon HDMI RX IP offers reliable implementation for HDMI interface, which can be integrated in the SOC used in multimedia device.
In each data channel, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The level-shifter changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. The input signals are reshaped by equalizer for frequency compensation. Then the serial stream is recovered and converted to 10-bit parallel output.
The PHY logic receives the recovered parallel data and clock signals of 3 data channels. These data are firstly synchronized to the same clock, then aligned to eliminate the channel skew and finally output to the controller for further process.
The HDMI receiver controller separates the incoming data stream into audio data, video data, and packet data information. The video interface can generate a variety of video formats including RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2, YCbCr 4:2:0. The receive audio interface includes up to four I2S output, for SPDIF outputs and a parallel audio output, providing support for HDMI 2.0 audio formats.
Innosilicon HDMI RX IP offers reliable implementation for HDMI interface, which can be integrated in the SOC used in multimedia device.
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