You are here:
Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel
This 12.5Gbps SERDES IP is designed for smooth integration of Multiple SERDES lanes offering best in class performance, area and power. The programmable PHY supports major standards such as PCIe Gen 1/2/3, USB 3.0 / 3.1, XAUI, SATA Gen 1/2/3, CEI-11G-LR, 10GBase-KX4, JESD204B, SGMII/QSGMII, RAPID I/O, HSSTP (Trace Port), V-By-One, DisplayPort and HMC.
查看 Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel 详细介绍：
- 查看 Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel 完整数据手册
- 联系 Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel 供应商
SERDES IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency