GSMC 0.13um 1.5v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. Its high speed VCO can run from 60MHz to 160MHz. The output frequency is from 30MHz to 80MHz. By setting PLL_DM [4:0] and PLL_DN [4:0] to different values according to different PLL_REFIN frequency, PLL_BAKO will be locked at the rising edge of PLL_REFIN and the output frequency PLL_CKO will be locked at the multiples of input frequency.

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